In the fabrication of light-emitting diodes (LEDs) and other high-performance devices such as laser diodes, optical detectors, and field effect transistors, a chemical vapor deposition (CVD) process is typically used to grow a thin film stack structure using materials such as gallium nitride over a sapphire or silicon substrate. A CVD tool includes a process chamber, which is a sealed environment that allows infused gases to be deposited upon the substrate (typically in the form of wafers) to grow the thin film layers. Examples of current product lines of such manufacturing equipment include the TurboDisc®, MaxBright®, and EPIK™ family of MOCVD systems, manufactured by Veeco Instruments Inc. of Plainview, N.Y. Another example is the PROPEL™ Power GaN MOCVD system, also by Veeco Instruments.
A number of process parameters are controlled, such as temperature, pressure and gas flow rate, to achieve a desired crystal growth. Different layers are grown using varying materials and process parameters. For example, devices formed from compound semiconductors such as III-V semiconductors typically are formed by growing successive layers of the compound semiconductor using metal organic chemical vapor deposition (MOCVD). In this process, the wafers are exposed to a combination of gases, typically including a metal organic compound as a source of a group III metal, and also including a source of a group V element which flow over the surface of the wafer while the wafer is maintained at an elevated temperature. Generally, the metal organic compound and group V source are combined with a carrier gas which does not participate appreciably in the reaction as, for example, nitrogen. One example of a III-V semiconductor is gallium nitride, which can be formed by reaction of an organo-gallium compound and ammonia on a substrate having a suitable crystal lattice spacing, as for example, a sapphire wafer. The wafer is usually maintained at a temperature on the order of 700-1200° C. during deposition of gallium nitride and related compounds.
In a MOCVD process chamber, semiconductor wafers on which layers of thin film are to be grown are placed on rapidly-rotating carousels, referred to as wafer carriers, to provide a uniform exposure of their surfaces to the atmosphere within the reactor chamber for the deposition of the semiconductor materials. Rotation speed is on the order of 1,000 RPM. The wafer carriers are typically machined out of a highly thermally conductive material such as graphite, and are often coated with a protective layer of a material such as silicon carbide. Each wafer carrier has a set of circular indentations, or pockets, in its top surface in which individual wafers are placed. Some examples of pertinent technology are described in U.S. Patent Application Publication No. 2012/0040097, U.S. Pat. No. 8,092,599, U.S. Pat. No. 8,021,487, U.S. Patent Application Publication No. 2007/0186853, U.S. Pat. No. 6,902,623, U.S. Pat. No. 6,506,252, and U.S. Pat. No. 6,492,625, the disclosures of which are incorporated by reference herein.
In some embodiments, the wafer carrier is supported on a spindle within the reaction chamber so that the top surface of the wafer carrier having the exposed surfaces of the wafers faces upwardly toward a gas distribution device. While the spindle is rotated, the gas is directed downwardly onto the top surface of the wafer carrier and flows across the top surface toward the periphery of the wafer carrier. The used gas is evacuated from the reaction chamber through ports disposed below the wafer carrier. The wafer carrier is maintained at the desired elevated temperature by heating elements, typically electrical resistive heating elements disposed below the bottom surface of the wafer carrier. These heating elements are maintained at a temperature above the desired temperature of the wafer surfaces, whereas the gas distribution device typically is maintained at a temperature well below the desired reaction temperature so as to prevent premature reaction of the gases. Therefore, heat is transferred from the heating elements to the bottom surface of the wafer carrier and flows upwardly through the wafer carrier to the individual wafers. In other embodiments, the wafer carrier can be supported and rotated by a rotation system that does not require a spindle. Such a rotation system is described in U.S. Patent Application Publication No. 2015/0075431, the contents of which are hereby incorporated by reference herein. In yet other embodiments, the wafer carrier holding at least one wafer is placed face down (inverted) in the reaction chamber and the gas distribution device is situated below the wafer carrier such that the process gases flow upwardly towards the at least one wafer. Examples of such inverted gas injection systems are described in U.S. Pat. No. 8,133,322, U.S. Patent Application Publication No. 2004/0175939, and U.S. Patent Application Publication No. 2004/0060518, the contents of which are hereby incorporated by reference herein.
In a MOCVD process, where the growth of crystals occurs by chemical reaction on the surface of the substrate, the process parameters must be controlled with particular care to ensure that the chemical reaction proceeds under the required conditions. Even small variations in process conditions can adversely affect device quality and production yield. For instance, if a gallium and indium nitride layer is deposited, variations in wafer surface temperature will cause variations in the composition and bandgap of the deposited layer. Because indium has a relatively high vapor pressure, the deposited layer will have a lower proportion of indium and a greater bandgap in those regions of the wafer where the surface temperature is higher. If the deposited layer is an active, light-emitting layer of an LED structure, the emission wavelength of the LEDs formed from the wafer will also vary to an unacceptable degree.
A great deal of effort has been devoted to system design features to minimize temperature variations of the wafers during processing. One challenge encountered in this effort relates to changes in surface profile of the wafers at various stages of processing. In an epitaxial growth process, the materials which form a semiconductor layer are deposited onto the surface of the substrate, forming a generally crystalline structure. The spacing between atoms within a crystal lattice (referred to as the “lattice spacing”) depends upon the composition of the crystal. Where the grown layer has a composition different from the composition of the substrate, the deposited layer may have a nominal lattice spacing, different from the lattice spacing of the substrate. In this case, the deposited crystalline layer forms with its lattice spacing stretched or compressed to conform to the lattice spacing of the substrate. As the grown layer is built up, the forces arising from the lattice mismatch at the surface of each wafer cause the wafer to deform.
The deformation tends to take a generally convex or concave shape, depending on the relative physical properties of the grown lattice and of the substrate material. The deformed shape of the wafers causes variations in spacing between the bottom of each wafer and the corresponding pocket floor of the wafer carrier. In turn, these spacing variations affect the heating uniformity of the wafers. This problem has been described in U.S. Pat. No. 7,570,368, the disclosure of which is incorporated by reference herein, which is each directed to measuring and estimating the curvature of wafer deformation. European Patent No. EP 2546600, the disclosure of which is also incorporated by reference herein, estimates a mean spherical curvature, as well as an azimuthal aspherical curvature deviation.
These approaches produce approximations of the curvature of each wafer based on collected measurements. However, in practice each wafer tends to deform in an irregular fashion. Thus, for example, rather than forming spherical bow or even a spherical bow with azimuthal deviation, which can be modeled based on a limited set of measurements, each wafer tends to bow in a unique, potato chip-like, form. Moreover, the extent and shape of deformation vary over the course of a process as the grown layers increase and as thermal conditions may vary in the reaction chamber.
A solution is needed to obtain a more accurate characterization of the in-process wafer deformation, for which various equipment or processing optimizations might be developed.